1. Field of the Invention
The present invention relates to a semiconductor memory.
2. Description of the Related Art
Generally, in the data read operation of a dynamic random access memory (DRAM) as a semiconductor memory, a predetermined data as stored is first transmitted from a memory cell to a sense amplifier through a column switch, thereby being amplified there. This amplified data is further transmitted to an output circuit and is then read out to the outside of the DRAM.
In a prior art DRAM, when transmitting the read data from the sense amplifier to the output circuit, the sense amplifier and the output circuit have been controlled by an address transition detection signal (referred to as "signal ATD" hereinafter) and a data read control signal (referred to as "signal WE" hereinafter).
In general, in case of the DRAM which includes a complementary data line provided between the sense amplifier and the output circuit, the sense amplifier is controlled by the signal ATD and signal WE, and the input of the read data to the output circuit is executed in response to the level transition of the complementary data line.
Recently, however, the ATD signal speed has been made higher in association with the access speed to the DRAM. Thus, in such a DRAM that its output circuit is controlled by the ATD signal in order to stabilize the input of the read data to the output circuit, it is needed to provide a delay circuit for delaying the ATD signal, in order to provide a predetermined margin for the input timing of the read data.
On one hand, in such a DRAM that the input of the read data to the output circuit is carried out in response to the level transition of the complementary data line, it is not necessary to provide any delay circuit for delaying the ATD signal. In this case, however, it is absolutely required to provide the complementary data line. Contrary to this, in case of a so-called single data line DRAM which is provided with no complementary data line for the purpose of reducing the chip area, such a delay circuit as mentioned above has to be provided inevitably.
Generally, in the DRAM, a plurality of sense amplifiers and output circuits are controlled in the same timing. Therefore, if the number of sense amplifiers and output circuits is increased to comply with the increase in the memory capacity, the noise generation caused when reading the data comes out as another problem to be concerned with.